Implementation of a Dual Analog Decoder

When considering forward error correction (FEC) algorithms for telecommunication applications, the BCJR algorithm is the sub-optimal MAP (maximum a posteriori) soft decoding algorithm. For the case of high code rate, BCJR decoding based on the trellis in the dual domain is computationally much less complex than in the original domain. Previously, designs of dual domain primitive circuit elements and high level simulations have been presented but no realization and validation have been reported. In this paper, we present the implementation of a dual analog decoder with high code rate. The implemented decoding algorithm performs three procedures which are branch weight generation, trellis calculation, and soft output generation. The Boxplus circuit performing multiplication and the current mirror are used as basic building blocks in the implementation. The decoder is simulated for a 16-length convolutional code with memory 1 and code rate 2/3. To validate the design we assumed a realistic channel environment and compared the physical circuit behavior (simulated in SPICE) with the algorithm level functionality (simulated in MATLAB). The SPICE simulation results indicate that each of the functional blocks has the distortion less than 3%. The implemented decoder has the same error correction performance as the one predicted by the high level simulations. In addition, the distorted behavior due to the non-ideal characteristic of physical devices is also discussed. Keywords—Forward Error Correction, BCJR Algorithm, Dual Domain, Analog Design.